The present invention relates to a semiconductor device and a method of manufacturing the same, and it is, for example, a technology applicable to a semiconductor device having a damascene wiring and a method of manufacturing the semiconductor device.
Various technologies related to wirings that configure a semiconductor device have been examined, and they include, for example, technologies described in International Publication No. WO 2007/078011 (Patent Document 1), Japanese Patent Laid-Open No. 2004-311477 (Patent Document 2), Japanese Patent Laid-Open No. 2007-123529 (Patent Document 3), Japanese Patent Laid-Open No. 2007-227958 (Patent Document 4), Japanese Patent Laid-Open No. 2007-281197 (Patent Document 5), Japanese Patent Laid-Open No. 2006-41039 (Patent Document 6), and Japanese Patent Laid-Open No. 2007-305755 (Patent Document 7). The technology described in Patent Document 1, after forming a via hole pattern in an insulating film structure, forms a groove pattern in a hard mask film, and performs groove processing in the above-described insulating film structure using the hard mask film as a mask. The technology described in Patent Document 2 is the one in which a mask for forming a wiring groove and a connection hole of a bottom of the wiring groove has a three-layer structure.
The technology described in Patent Document 3 couples divided trenches to each other by a via hole. The technology described in Patent Document 4 is the one in which a silicon-containing metal wiring that does not include a metal silicide layer is used as a metal wiring. The technology described in Patent Document 5 removes an interlayer insulating film serving as a mask in forming a wiring layer and forms a via hole over the wiring layer. The technology described in Patent Document 6 removes a part of an insulating film to make a via hole penetrate by dry etching in which a mixed gas containing a fluorine compound gas and a nitrogen-containing gas is used for an etching gas, and in which a pressure of the mixed gas in an etching treatment chamber is controlled in a range of 0.1 Pa to 6.0 Pa. In addition, the technology described in Patent Document 7 forms a hydrophobic first insulating film and a hydrophilic second insulating film as insulating films that configure a multilayer wiring structure.